Impact of Substrate Noise on Analog Design
نویسندگان
چکیده
This paper presents the analysis and measurements of the impact of digital substrate noise on embedded Analog-to-Digital converters. The impact of substrate noise on analog design is explained, followed by a specific entire impact analysis of the impact on a regenerative comparator and an A/D converter. To confirm the analysis the substrate noise has also been measured on a test chip designed in a 0.35 μm heavily–doped-substrate CMOS technology. From the measurements it was deduced that SNR and the effective number of bits are reduced by 20%. Index terms – substrate noise, ADC, impact measurement, jitter.
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